Design Engineer
Description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Custom Layout Design Engineer
Position Description:
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Responsible for custom layout floorplan, matching guides, resistor/capacitor placement, reduce coupling & noise, sensitive signals routing, mix-signals routing, etc.
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Responsible for custom layout top level hierarchy floorplan for blocks/powers
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Responsible for high-speed mixed-signal PHY such as SerDes, USB, DDR, etc
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Responsible for cooperation with analog circuit design team to ensure high efficiency and quality for analog layout design.
Position Requirements:
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BSEE degree with 2+ years of applicable experience in analog/custom layout of advanced technology nodes
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Proficient with Layout edit/verify tools, like Virtuoso XL, Pegasus/Calibre DRC/LVS, etc.
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Proficient with EMIR tools, like Voltus-FI
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Hands-on experience conducting DRC/LVS/ERC analysis, EMIR analysis, and recommending appropriate solutions
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Fundamental understanding of IC design technology and process/methodology
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Essential that the individual demonstrates good teamwork and self-motivation
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Good communication skills in English
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Work experience in PERC run is a plus
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Work experience in FinFET layout is a plus
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Work experience in ESD/Latch-up is a plus
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Work experience in cooperation with digital P&R team is a plus