Staff Verification Design Engineer
Description
Responsibilities
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Perform block and chip-level verification in register-transfer level (RTL), gate-level and analog/mixed-signal (AMS).
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Run digital/mixed-signal simulations as well as formal verification.
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Work closely with the design team to create verification strategy and detailed verification plan.
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Develop tests, run regressions and monitor coverage to ensure tape-out quality.
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Participate in design or project reviews and support these with verification perspective and schedule/priority assessment.
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Support post-silicon bring-up and debug, for bench validation as well as automated test equipment (ATE) testing.
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Improve verification scalability and portability from project to project by environment enhancement and tools automation.
Minimum Qualifications
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3+ years experience in semiconductor industry
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M.S. in EE/CS/CE or higher
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Hands-on experience with System Verilog as High-level Verification Language and UVM implementation.
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Debugging digital simulation in both RTL and gate-level netlist, isolating issues in both module and system level.
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Scripting experience in Python or Perl.
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Clear understanding of ASIC design flow
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Solid analytical, synthesis and problem solving skills
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Independent, self-motivated, rigorous, team player and able to follow through
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Excellent verbal and written communication skills
Desired Qualifications
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Experience of setting up UVM verification environment from scratch
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Familiarity with VHDL or System Verilog RNM
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Automation of verification flow with Python/Perl in industrial setting
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Analog behavioral model development/verification experience