Senior AI STA Engineer, Sub-chip
Description
NVIDIA is looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you'll be doing:
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Perform advanced AI Static Timing Analysis (STA) for complex chiplet and full chip level.
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AI use for timing optimization and data analysis in STA and PnR .
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Running and build STA tools for anlyaze and debug timing .
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Use traditional STA tools like Prime Time, review and debug timing paths, understand constraints, sdc generation, timing ecos generation.
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Identify convergence risks and work closely with physical design, RTL and DFT teams, ensuring convergence throughout various project stages.
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Responsible for a full timing closer and quality approval from pre-layout STA model through signoff.
What we need to see:
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B.SC./ M.SC. in Electrical Engineering.
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At least 5+ years of hands-on STA experience.
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Experience in Prime Time and signoff methodologies.
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A great teammate who thrives in a collaborative environment.
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AI tools orientation or alternatively a desire to learn.
Ways to stand out from the crowd:
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Agentic Frameworks.
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AI prompting experience.
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Experience in Linux environments.
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TCL, Python, shell scripting abilities.
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Experience with data collection and analysis.
NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry!